Each Luminosity Monitor (LM) detector will have 24 Hamamatsu R5505 fine-mesh photomultiplier tubes (PMT).
Each PMT anode signal shall be optionally amplified at the detector should it be necessary to reduce noise pickup. The amplifier will have a gain of 10, a rise time that is less than 1.5 ns, and wideband noise less than 50 mV referred to the input.
The amplified PMT signals will be brought to the LM platform racks on existing RG-58 cables used by the Level 0 trigger.
Platform Electronics
Existing NIM crates in platform racks ??? and ??? will be used to house the LM platform electronics. One NIM crate is required in each rack, with each crate containing the following modules:
2 Phillips Model 776 NIM 16 channel Photomultiplier Preamp modules.
5 Phillips Model 715 NIM 5 channel Constant Fraction Discriminator modules.
1 crate voltage monitoring module.
Each PMT signal will be amplified with a gain of 10 by the PMT preamp modules. These modules provide two signal outputs; one output will be used for monitoring the photomultiplier gain using the muon scintillator electronics and the other output will be used be used to make a precise timing measurement.
The timing output will be discriminated by the Constant Fraction Discriminator.
The discriminated signal will be sent to the LM Moving Counting House (MCH) rack ??? on new RG-?? cables of length ??.
The monitoring output will be sent to muon scintillator electronics racks ???? and ???? using RG-58 cables of length ??.
The NIM crate voltages will be monitored through a 1553. Rack Monitor Interfaces will be installed in the platform racks to provide the appropriate safety interlocks.
MCH Electronics
An existing NIM crate mounted in rack ??? will be used for any auxiliary trigger logic that may become necessary.
An existing VME crate mounted in rack ??? will be used to house the LM readout electronics. The following boards are expected to be located in the VME crate:
1 Vertical Interconnect board that provides the interface to the slow-control network.
1 VBD board that serves as the interface to the data acquisition system.
2 LM TDC boards that will digitize and process the discriminated LM signals as described below.
1 LM Controller board that will provide a variety of functions as described below.
1 Berkeley Nucleonics B950 digital delay generator for use in calibrating the TDC slopes.
1 Bit 3 Model ???? VME to PCI adapter with fiber optic data links for transferring data between the LM VME crate and the LM monitor computer.
The NIM and VME crate voltages will be monitored through a 1553. A Rack Monitor Interface will be installed in the MCH rack to provide the appropriate safety interlocks.
LM TDC Board
Each LM TDC board will have 24 front panel photomultiplier inputs and 4 front panel auxiliary inputs for timing other signals.
Each LM TDC board will have the following front panel fast inputs:
TDC common stop.
TDC reset.
TDC common start used for TDC calibration.
7.59 MHz tick clock.
Each LM TDC board will have the following identical set of signals provided to its J3 VME bus connection:
Beam Present signal to indicate presence of beam in the IR for this tick.
Turn signal to indicate start of a new turn.
Initialize signal to indicate L2 and readout queues should be initialized.
L1 Accept signal to indicate a L1 trigger.
L2 Decision signal to indicate a L2 decision has been made.
L2 Accept signal to indicate a L2 trigger.
Each LM TDC board will provide the following signals on its J2 VME bus connection:
Average time of valid hits (8 bits).
Multiple interaction measure for this channel (8 bits).
TDC monitor output (10 bits shared by the LM TDC boards).
Interaction signal to indicate the presence of one or more in-time hits (1 bit).
Halo signal to indicate the presence of one or more early "halo" hits (1 bit).
Time for forward proton spectrometer hit (6 bits).
Valid forward proton spectrometer hit (1 bit).
Valid hit for small acceptance luminosity calculation (1 bit).
Level 2 Error signal to indicate L2 queue overflow, L2 queue underflow, or L2 accept with a full readout queue (1 bit).
Each timing channel will have a time-to-analog converter, similar to the one used on the Level 0 QTAC boards, with the analog output digitized by a 10 bit ADC. The digitized output will measure the time in approximately 25 ps units and have a measurement range of approximately 25 ns.
Each time-to-analog converter will be started by either a logic signal from the front panel signal inputs or the TDC common start signal. The converter will be stopped by the TDC common stop signal.
All TDC outputs will be fed into a FPGA, which will perform the following tasks:
Calibration according to the formula t_cal = slope * (TDC - T0).
Identification of valid and halo hits for photomultiplier signals based on the value of t_cal.
Generation of interaction and halo signals.
Calculation of the average time for valid hits.
Calculation of the average time for halo signals.
Calculation of the multiple interaction measure.
Saving the following data in queues of fixed length queues pending the L1 trigger decision:
TDC output for each channel.
Calibrated time for each channel.
Average time for valid hits.
Multiple interaction measure.
Interaction signal.
Halo signal.
Following an L1 accept, moving all saved data into a 16 deep FIFO queue pending the L2 trigger decision.
Following an L2 accept, moving all saved data into a 16 deep FIFO readout queue.
Initialize the following FPGA parameters that are stored in non-volatile RAM:
T0 for each TDC channel.
Slope for each TDC channel.
Minimum valid time.
Maximum valid time.
Minimum halo time.
Maximum halo time.
Length of the L1 trigger pending queue.
Putting one of the following pieces of data on the TDC monitor output lines, as selected by the TDC monitor output data source selector:
TDC raw data for a selected channel.
Calibrated time for a selected channel.
Number of valid time hits.
Number of halo hits.
Average time for valid hits.
Average time for halo hits.
Multiple interaction measure.
Interface the VME bus to the output of the readout queues, the contents of the L1 pending, L2 pending, and readout queues, the pointers for the L2 pending and readout queues, the TDC monitor output data source selector, and the non-volatile RAM.
If space is available, a scratch area will be provided on the board containing the un-assigned FPGA pins and space for additional logic circuits.
LM Controller Board
High Voltage
Six standard D0 HV supplies, each with 8 HV channels, will be used to provide independently controllable HV to the 48 PMTs. The LM HV supplies will occupy one crate in rack ???.
?? type ?? fanout boxes will be mounted in rack ?? to patch the 48 HV outputs onto 8 existing HV cables that were used for the Level 0 detector. Each 8-conductor cable will carry 6 HV channels.
Each LM detector assembly will have 2 standard D0 Reynolds HV connectors that then distribute the HV to the 12 PMTs in the LM detector assembly.